By analyzing the parasitic characteristics of vias, we can see that in high-speed PCB design, the seemingly simple vias often have a significant negative effect on the design of the circuit. In order to reduce the adverse effects of the parasitic effect of vias, the design can try to.
1, from both the cost and signal quality considerations, choose a reasonable size of the vias size. For example, for 6-10 layers of memory module PCB design, the choice of 10/20Mil (drill / pad) vias better, for some high-density small size board, you can also try to use 8/18Mil vias. Under the current technical conditions, it is difficult to use smaller size vias. For power or ground vias can be considered to use larger sizes to reduce impedance.
2, the two formulas discussed above can be derived from the use of a thinner PCB board to reduce the two parasitic parameters of the vias.
3, the signal alignment on the PCB board as far as possible without changing layers, that is, try not to use unnecessary vias.
4, the power supply and ground pins should be punched close to the over-hole, the shorter the lead between the over-hole and the pin, the better, because they can lead to an increase in inductance. Also the power and ground leads should be as thick as possible to reduce impedance.
5. Place some grounded vias near the vias of the signal change layer in order to provide the nearest circuit for the signal. You can even place a large number of extra grounded vias on the PCB board. Of course, in the design also needs to be flexible and versatile. The previously discussed vias model is the case of each layer has pads, there are times when we can reduce or even remove the pads of some layers. Especially in the case of a very high density of vias, which may lead to the formation of a circuit break in the copper layer, to solve such problems in addition to moving the location of the vias, we can also consider reducing the size of the vias in the copper layer of the pads.